In network communications, when many network protocols are implemented, a corresponding storage address needs to be found in an address table based on input data (referred to as a key), and target data in the storage address is obtained. For example, when a switch receives a data frame from an interface, the switch extracts a destination media access control (MAC) address of the data frame, searches an address table based on the destination MAC address to obtain a corresponding storage address, and then reads a forwarding entry corresponding to the storage address to obtain a corresponding port and forwards the data frame to the port.
Currently, an FPGA in a switch is usually used to perform the function of searching an address table. When the address table is of a relatively large size, the address table is stored in a content addressable memory (CAM) that is connected to the FPGA and that supports parallel search. However, the CAM features large power consumption and high costs. In some scenarios in which an address table is of a relatively small size (for example, with less than one thousand (1 k) entries) but there is a relatively large bandwidth (that is, scenarios in which a large quantity of packets need to be processed per unit time), the FPGA needs to access the CAM frequently per unit time. In this case, deploying the CAM outside the FPGA leads to high costs, and fast search cannot be implemented.